The IC 24LC01/24LC02 uses the I2C addressing proto- col and 2-wire serial interface which includes a bidirec- tional serial data bus synchronized by a clock. Microchip 24LC02 EEPROM are available at Mouser Electronics. Mouser offers inventory, pricing, & datasheets for Microchip 24LC02 EEPROM. Description, Bit/Bit Serial EePROM Write Protect Memory Chips. Company, Pronics. Datasheet, Download 24LC02 datasheet. Quote. Find where to.

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After this period the first clock pulse is generated. A read operation is initi- ated if this bit is high and a write operation is initiated if this bit is low. The datasjeet address word consist of a mandatory one, zero sequence for the first four most significant bits refer to the diagram show- ing the Device Address.

Input Capacitance See Note. After 24lcc02 the 8-bit data word, the EEPROM will output a zero and the address- ing device, such as a microcontroller, must terminate the write sequence with a stop con- dition.

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Internally organized with 8-bit words, the 1K requires a 7-bit data word address for random word addressing. Stresses exceeding the range specified under “Absolute Maxi. Data transfer may be initiated only when the. Instead, after the EEPROM ac- knowledges the receipt of the first data word, the microcontroller can transmit up to seven more data words.


Write operation with built-in timer. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Serial clock data input.

Clock and data transition. Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle.

These three bits must compare to dtasheet corresponding hard-wired input pins. A write operation requires an 8-bit data word address following the device address word and acknowledgment. Partial page write allowed.

If not, the chip 24lc002 return to a standby state. These are stress ratings only. For relative timing, refer to timing diagrams. During data transfer, the data line must remain stable whenever the clock line is high.

Time in which the bus must be free before a new transmission can start. If the device is still busy with the. Search field Part name Part description.

Commerical temperature range 0.

Document Outline

Hardware controlled write protection. Output Capacitance See Note. The device is optimized for use in many industrial and com.

Output Valid from Clock. The microcontroller must terminate the page write sequence with a stop condition.


24LC02 (HOLTEK) PDF技术资料下载 24LC02 供应信息 IC Datasheet 数据表 (4/8 页)

ACK polling can be initiated immediately. Data Input Setup Time. Internally organized with 8-bit words, the 2K requires an 8-bit data word address for random word addressing.

Upon receipt of this ad- dress, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. A page write is initiated the same as byte write, but the microcontroller does not send a stop condition after the first data word is dxtasheet in.

Since the datasheef will not acknowledge during a write cycle, this can be used to determine when the cycle is complete this feature can be used to maximize bus throughput. The pin is open-drain driven and may be wired-OR with any number of other open-drain or open collector devices.

Data Input Hold Time. Characteristics Functional Description Timing Diagrams.

24LC02 PDF Datasheet浏览和下载

The higher data word address bits are not incremented, re- taining the memory page row location refer to Page write timing.

The SDA pin is bidirectional for serial data transfer. This happens during the ninth clock cycle.